1. Technical Field
The invention generally relates generally to a calculation circuit and method for the division of a fixed-point input signal and, in particular, to a circuit and method for dividing a digital fixed-point input signal by an adjustable division factor 2a for generating a divided fixed-point output signal that comprises minimal variance.
2. Discussion of Related Art
DE 690 30 772 T2 describes a divider for high-speed execution of an arithmetic operation. The divider serves for generating a quotient by dividing a dividend by a divisor. A first holding device contains the dividend data characterizing the dividend. A second holding device contains the divisor data characterizing the divisor. An operation device generates either a sum or a difference between the dividend data and the divisor data. The divider furthermore contains a third holding device which serves for holding sign bit data. An inverting device is provided for inverting the sign bit data. The divider furthermore contains a shift device for sequentially shifting the inverted sign bit data from a least significant bit position, if the inverted sign bit data are input from the inverting device, while the inverted sign bit data are held. A further shift device is provided for arithmetically shifting the result data generated by the operation device by one bit toward the left, while a logic ZERO is stored in an LSB position. A control device serves for controlling the execution of the iterative division processing through the control of the operation device and of the two shift devices, with the result that the operation device generates the sum or difference on the basis of the buffer-stored sign bit data. The second shift device doubles the operation result generated by the operation device, the first holding device buffer-storing the doubled result.
DE 695 04 192 T2 describes a circuit arrangement for the digital implementation of a division operation according to a method of ignoring intermediate remainders.
In many applications, it is necessary to divide a fixed-point signal comprising a sequence of digital data values having a width of n bits by a fixed division factor.
FIG. 1 shows a calculation circuit for the division of a fixed-point input signal present by an adjustable division factor for the purpose of generating a divided fixed-point output signal according to the prior art. The conventional fixed-point division circuit shown in FIG. 1 comprises a signal input E for applying the fixed-point input signal to be divided. In this case, the fixed-point input signal comprises a sequence of digital data values that have a width of n bits and are applied to the signal input E of the fixed-point division circuit via n data lines.
Via internal data lines of the fixed-point division circuit, the sequence of digital data values having a width of n bits passes to an addition circuit ADD, which adds the digital data value of the fixed-point input signal present to a data value buffer-stored in a register R. The register R is connected to the addition circuit ADD via a data lines for outputting a buffer-stored digital data value having a width of a bits. The addition circuit ADD adds the digital data value of the fixed-point input signal present to the data value having a width of a bits, said data value being buffer-stored in the register R, to form a summation data value having max (n,a)+1 data bits. The summation data value is output via data lines to a signal input of a split circuit SPLIT.
The split circuit splits the summation data value (which comprises a width of max(n,a)+1 bits) into a first data value, comprising the a less significant data bits of the summation data value, and into a second data value, comprising the more significant data bits of the summation data value. The first data value is output via max(n,a)−a+1 data lines at a signal output A of the fixed-point division circuit. The noise inflicted by the fixed-point division circuit can be filtered out by a downstream digital filter. The second data value is buffer-stored via a data lines in the register R and fed back to the addition circuit ADD.
The method of operation of the fixed-point division circuit of FIG. 1 will now be explained using an example. In this example, the fixed-point division circuit divides the fixed-point input signal present by a division factor 4, the number of fed-back less significant data bits of the second data value output by the split circuit being a=2. If a constant signal sequence comprising digital data values which have a width of 4 bits and have the value 3 (3=0011) in a constant manner is applied to the signal input E of the fixed-point division circuit, the following sequence of data values is produced in the case of the fixed-point division circuit according to the prior art as is illustrated in FIG. 1:
TABLE 1E3333 3333 . . .R0321 0321 . . .A0111 0111 . . .
From the output data sequence A, the average value of the output signal is calculated in a downstream calculation circuit, said average value being 0.75 in the example illustrated. The constant input signal having the value 3 is divided by the division factor 4 by the fixed-point division circuit to form the value ¾=0.75.
The conventional fixed-point division circuit of FIG. 1 has a disadvantage, however, that in the case of an alternating input signal, the variance of the fixed-point output signal output by the fixed-point division circuit increases. By way of example, if an alternating signal sequence having alternate digital data values +3, −3 is applied to the signal input E of the fixed-point division circuit according to the prior art, the following data sequence is produced. The negative data values are represented as two's complement in a binary manner, i.e. the positive data value +3 corresponds to the binary value 0011 and the negative data value −3 corresponds to the binary coded data value 1101.
TABLE 2E+3 −3 +3 −3 +3 −3 +3 −3R1 1 1 1 0 0 0 0A+1 −1 +1 −1 +1 −1 +1 −1
As can be discerned, when an alternating input signal is present, the conventional fixed-point division circuit outputs an output signal that fluctuates back and forth between the digital value +1 and −1. Consequently, the variance of the output signal is not zero.
When a conventional fixed-point division circuit of this type is used in a feedback control loop, the value output by the fixed-point division circuit will fluctuate and thus reduce the stability of the closed-loop control.